1. Field of the Invention
The present invention relates to a semiconductor device suitable for a ferroelectric memory and a manufacturing method of the same.
2. Description of the Related Art
In recent years, the development of a ferroelectric memory (FeRAM) which holds information in a ferroelectric capacitor using polarization inversion of a ferroelectric has been advanced. The ferroelectric memory is a nonvolatile memory in which held information is not erased even if the power is turned off, and attracts special attention because it can realize high-density integration, an increase in driving speed, an improvement in durability, and a reduction in power consumption.
As materials for a ferroelectric film composing the ferroelectric capacitor, ferroelectric oxides having a perovskite crystal structure such as PZT(Pb(Zr, Ti)O3)), SBT(SrBi2Ta2O9), and the like are mainly used. These materials can obtain a remanent polarization amount as large as approximately 10 μC/cm2 to 30 μC/cm2. However, regarding such a ferroelectric film, it is known that ferroelectric characteristics deteriorate due to moisture which has penetrated from the outside through an interlayer insulating film such as a silicon oxide film having a high affinity to moisture. The moisture which has penetrated into the ferroelectric memory (semiconductor device) from the outside is decomposed into hydrogen and oxygen during a high-temperature process when the interlayer insulating film and a metal wiring are formed. Then, the hydrogen which has reached the ferroelectric film reacts with oxygen in the ferroelectric film to cause oxygen deficiency to the ferroelectric film, which results in a reduction in crystallinity.
Moreover, if a ferroelectric memory is used over a long period of time after being manufactured, in some cases, the remanent polarization amount and dielectric constant of the ferroelectric film reduce accompanying the penetration of hydrogen, and thereby the performance of the ferroelectric capacitor deteriorates. Such a deterioration in performance occurs not only in the ferroelectric capacitor but also in other semiconductor elements such as a transistor.
FIG. 19 shows a general view of a semiconductor circuit on which general logic circuits or ferroelectric capacitors are mounted. It shows a multi-tip structure, in which plural chips are formed in one shot. FIG. 20 shows an enlarged view of one chip. As shown in FIG. 20, one chip is partitioned into a PAD section located at an outer periphery of the chip and a circuit section located inside the PAD section. In the case of a product in which both the logic circuit and the ferroelectric capacitor are mounted, the circuit section is further partitioned into a FeRAM section and a logic section. FIG. 21 shows a layout of a section taken along the line X-Y in FIG. 20. From the X side, this chip is partitioned into a scribe section 501, a scribe section-PAD section boundary section 502, a PAD section 503, a PAD section-circuit section boundary section 504, a FeRAM section (cell section) 505, a circuit-circuit boundary section 506, a logic section 507, a PAD section-circuit section boundary section 508, a PAD section 509, a scribe section-PAD section boundary section 510, and a scribe section 511. Outside the scribe sections 501 and 511 are regions for other chips.
FIG. 22 is a sectional view showing the structure of the PAD section (a sectional view taken along the line A-B) of the semiconductor circuit on which the general logic circuit or the ferroelectric capacitor is mounted. As shown in FIG. 22, a silicon oxide film 522 and a silicon nitride film 523 are formed as a passivation film on a PAD wiring portion (wiring portion 526), and a polyimide layer (PI layer) 524 is formed thereon. The PAD wiring portion 526 is formed on a wiring portion 521 with wiring contact portions 525 therebetween. A silicon oxide film 527 is formed between the wiring portion 521 and the PAD wiring portion 526. Such a structure is a general PAD structure, but this PAD structure has the following problems.
First, the silicon oxide film 522 does not have a moisture and hydrogen barrier function, and if anything, it has hygroscopicity. Accordingly, when the silicon oxide film 522 is exposed to the surface, it allows moisture and hydrogen to permeate therethrough.
Secondly, the silicon nitride film 523 has a moisture barrier function to some extent, but allows hydrogen to permeate therethrough. If the silicon nitride film 523 is thickened simply in order to prevent moisture, a moisture barrier property is correspondingly improved. However, gas (for example, ammonia) containing a hydrogen group is used in the process of forming the silicon nitride film 523, whereby the ferroelectric capacitor deteriorates due to the influence thereof. Therefore, the silicon nitride film cannot be thickened excessively.
Thirdly, similarly to the silicon oxide film 522, the polyimide layer 524 has no moisture and hydrogen barrier property.
Hence, the following events occur in conventional PAD section structure and circuit section structure.
(A) Moisture and hydrogen penetrate into the PAD section.
(B) Hydrogen and a little moisture penetrate into the circuit section.
Namely, in the conventional PAD section structure, the penetration of moisture and hydrogen cannot be fully prevented. Moreover, as shown in FIG. 23, the silicon nitride film 523 may crack.
To improve these problems, a technique for preventing the penetration of moisture and hydrogen by using a metal film is disclosed in Patent Documents 1 and 4. A principal structure thereof is shown in FIG. 24. A metal wiring 532, an insulating film 533, a passivation film 534, and a bonding pad 535 are formed on an interlayer insulating film 531. This structure is characterized in that a metal PAD section is further formed on the PAD section to prevent the silicon oxide film above the PAD section from being exposed. However, even in this structure, the following events occur.
(A) No moisture penetrates into the PAD section. The hydrogen barrier property is high because of a metal film. However, in actuality, a sidewall of the metal PAD section on the PAD section easily cracks. Moreover, when the structure of such a publicly known example is adopted, it is necessary that after the metal PAD section is formed thick, it is subjected to CMP processing to be planarized or subjected to plating. But, this is not described in Patent Documents 1 and 4. Accordingly, the structure formed by the method described in Patent Documents 1 and 4 is as shown in FIG. 25. Further, a structure shown in FIG. 26 is disclosed as the structure obtained after the CMP processing, but in the case of this structure, micro-scratches are generated in the passivation film (silicon nitride film) 534 at the time of the CMP processing of the PAD section.
(B) A little moisture and hydrogen as it is penetrate into the circuit section.
(C) Since the passivation film is used as an etching stopper when the second metal film is formed, irregularities occur on the surface, and hydrogen easily penetrates from its microscopic irregular portions.
A technique for preventing the penetration of moisture and hydrogen is disclosed also in Patent Document 2. A principal structure thereof is shown in FIG. 27A and FIG. 27B. An aluminum film 542, an interlayer film 543, an aluminum film 544, and a cover film 545 are formed on a semiconductor substrate 541, and a bonding wire 546 is connected to the aluminum film 544. In this structure, the PAD section is entirely coated with the metal film (aluminum film 544), but the following events occur.
(A) No moisture penetrates into the PAD section. A method of forming the aluminum film 544 is not described, but by adopting such a structure, only in the PAD section, the penetration of moisture is eliminated and the penetration of hydrogen is reduced.
(B) There is no description of the circuit section, but considering a technical level of those days, it is thought that the circuit section has a structure such as shown in FIG. 28. In this structure, moisture and hydrogen penetrate from above.
A technique for preventing the penetration of moisture and hydrogen is disclosed also in Patent Document 3. A principal structure thereof is shown in FIG. 29. An interlayer insulating film 552, a pad metal film 553, a PSG film 554, a silicon nitride film 555, and a metal film 556 are formed on a semiconductor substrate 551. In this structure, the PAD section is entirely coated with the metal film 556, but the following events occur.
(A) Since the PAD section is coated with the metal film 556, no moisture penetrates thereinto. However, when the metal film 556 is an aluminum film, its hydrogen barrier property is not so high, whereby a little hydrogen penetrates. Further, since the metal film 556 on a sidewall of the PAD section cannot be formed thick by a sputtering method, there is a possibility that a crack opens later.
(B) There is no description of the circuit section, but considering a technical level of those days, it is thought that the circuit section has a structure such as shown in FIG. 30. In this structure, moisture and hydrogen penetrate from above.
As just described, even if these conventional techniques are adopted, it is extremely difficult to fully inhibit deterioration of the ferroelectric capacitor or the like accompanying the penetration of moisture.
The related arts are disclosed in Patent Document 1 (Japanese Patent Application Laid-open No. Hei 10-92817), Patent Document 2 (Japanese Patent Application Laid-open No. Hei 6-69270), Patent Document 3 (Japanese Patent Application Laid-open No. Hei 4-58531), and Patent Document 4 (Japanese Patent No. 3305211).